Verification Engineer

Focus Areas

Focus areas include but are not limited to: RTL and system-level verification, UVM, assertions, coverage, debug.

Strong Verilog/SystemVerilog and UVM skills
RTL debug skills
Processor/SoC experience
RISC-V experience preferred
Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

We have multiple openings.

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